Low Truncation Error and Area Efficient Multiplier for Cryptographic Applications

Multipliers play a vital role in many cryptographic applications like elliptic curve cryptography, RSA and other algorithms. The direct truncation of least significant part of the product leads to large error in the resultant product when fixed width output is the requirement. This paper proposes a truncation error minimizing logic which greatly reduces truncation error. Truncation error minimizing logic has been inserted in the least significant part of full length Baugh Wooley multiplier and Modified Booth Recoding multiplier and the results are compared.VHDL simulation shows that the truncation error is reduced up to 68% compared with direct truncated multiplier and involves lesser number of gates when compared to full length multipliers. It is also found that the total power consumed by these multipliers is only half the amount consumed by full length multiplier. Also Baugh Wooley multiplier performs better than Modified Booth Recoding multiplier. General Terms Fixed width multiplier, Vhdl modeling of truncation error minimizing logic.